Multi-processor system-on-chip. (Record no. 12783)
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| 001 - CONTROL NUMBER | |
| control field | on1243532832 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | OCoLC |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20240523125543.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS | |
| fixed length control field | m o d |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION | |
| fixed length control field | cr un|---aucuu |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 210327s2021 enk o 000 0 eng d |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | EBLCP |
| Language of cataloging | eng |
| Description conventions | pn |
| Transcribing agency | EBLCP |
| Modifying agency | DG1 |
| -- | OCLCO |
| -- | YDX |
| -- | UKAHL |
| -- | OCLCF |
| -- | OCLCQ |
| -- | OCLCO |
| -- | OCLCQ |
| -- | UPM |
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| -- | WSU |
| -- | OCLCL |
| 019 ## - | |
| -- | 1242577731 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9781119818298 |
| Qualifying information | (electronic bk. ; |
| -- | oBook) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 111981829X |
| Qualifying information | (electronic bk. ; |
| -- | oBook) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9781119818274 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 1119818273 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Canceled/invalid ISBN | 9781789450217 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Canceled/invalid ISBN | 1789450217 |
| 029 1# - OTHER SYSTEM CONTROL NUMBER (OCLC) | |
| OCLC library identifier | AU@ |
| System control number | 000069138768 |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (OCoLC)1243532832 |
| Canceled/invalid control number | (OCoLC)1242577731 |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER | |
| Classification number | TK7895.E42 |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 006.2/2 |
| Edition number | 23 |
| 049 ## - LOCAL HOLDINGS (OCLC) | |
| Holding library | MAIN |
| 245 00 - TITLE STATEMENT | |
| Title | Multi-processor system-on-chip. |
| Number of part/section of a work | 1, |
| Name of part/section of a work | Architectures / |
| Statement of responsibility, etc. | coordinated by Liliana Andrade, Fr�ed�eric Rousseau. |
| 246 30 - VARYING FORM OF TITLE | |
| Title proper/short title | Architectures |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Place of publication, distribution, etc. | London : |
| Name of publisher, distributor, etc. | ISTE, Ltd. ; |
| Place of publication, distribution, etc. | Hoboken : |
| Name of publisher, distributor, etc. | Wiley, |
| Date of publication, distribution, etc. | 2021. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 1 online resource (321 pages) |
| 336 ## - CONTENT TYPE | |
| Content type term | text |
| Content type code | txt |
| Source | rdacontent |
| 337 ## - MEDIA TYPE | |
| Media type term | computer |
| Media type code | c |
| Source | rdamedia |
| 338 ## - CARRIER TYPE | |
| Carrier type term | online resource |
| Carrier type code | cr |
| Source | rdacarrier |
| 588 0# - SOURCE OF DESCRIPTION NOTE | |
| Source of description note | Print version record. |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Cover -- Half-Title Page -- Dedication -- Title Page -- Copyright Page -- Contents -- Foreword -- Acknowledgments -- PART 1: Processors -- 1 Processors for the Internet of Things -- 1.1. Introduction -- 1.2. Versatile processors for low-power IoT edge devices -- 1.2.1. Control processing, DSP and machine learning -- 1.2.2. Configurability and extensibility -- 1.3. Machine learning inference -- 1.3.1. Requirements for low/mid-end machine learning inference -- 1.3.2. Processor capabilities for low-power machine learning inference -- 1.3.3. A software library for machine learning inference |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | 1.3.4. Example machine learning applications and benchmarks -- 1.4. Conclusion -- 1.5. References -- 2 A Qualitative Approach to Many-core Architecture -- 2.1. Introduction -- 2.2. Motivations and context -- 2.2.1. Many-core processors -- 2.2.2. Machine learning inference -- 2.2.3. Application requirements -- 2.3. The MPPA3 many-core processor -- 2.3.1. Global architecture -- 2.3.2. Compute cluster -- 2.3.3. VLIW core -- 2.3.4. Coprocessor -- 2.4. The MPPA3 software environments -- 2.4.1. High-performance computing -- 2.4.2. KaNN code generator -- 2.4.3. High-integrity computing |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | 2.5. Conclusion -- 2.6. References -- 3 The Plural Many-core Architecture -- High Performance at Low Power -- 3.1. Introduction -- 3.2. Related works -- 3.3. Plural many-core architecture -- 3.4. Plural programming model -- 3.5. Plural hardware scheduler/synchronizer -- 3.6. Plural networks-on-chip -- 3.6.1. Scheduler NoC -- 3.6.2. Shared memory NoC -- 3.7. Hardware and software accelerators for the Plural architecture -- 3.8. Plural system software -- 3.9. Plural software development tools -- 3.10. Matrix multiplication algorithm on the Plural architecture |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | 4 ASIP-Based Multi-Processor Systems for an Efficient Implementation of CNNs -- 4.1. Introduction -- 4.2. Related works -- 4.3. ASIP architecture -- 4.4. Single-core scaling -- 4.5. MPSoC overview -- 4.6. NoC parameter exploration -- 4.7. Summary and conclusion -- 4.8. References -- PART 2: Memory -- 5 Tackling the MPSoC DataLocality Challenge -- 5.1. Motivation -- 5.2. MPSoC target platform -- 5.3. Related work -- 5.4. Coherence-on-demand: region-based cache coherence -- 5.4.1. RBCC versus global coherence -- 5.4.2. OS extensions for coherence-on-demand -- 5.4.3. Coherency region manager |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | 5.4.4. Experimental evaluations -- 5.4.5. RBCC and data placement -- 5.5. Near-memory acceleration -- 5.5.1. Near-memory synchronization accelerator -- 5.5.2. Near-memory queue management accelerator -- 5.5.3. Near-memory graph copy accelerator -- 5.5.4. Near-cache accelerator -- 5.6. The big picture -- 5.7. Conclusion -- 5.8. Acknowledgments -- 5.9. References -- 6 mMPU: Building a Memristor-based General-purpose In-memory Computation Architecture -- 6.1. Introduction -- 6.2. MAGIC NOR gate -- 6.3. In-memory algorithms for latency reduction -- 6.4. Synthesis and in-memory mapping methods |
| 500 ## - GENERAL NOTE | |
| General note | 6.4.1. SIMPLE. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc. | A Multi-Processor System-on-Chip (MPSoC) is the key component for complex applications. These applications put huge pressure on memory, communication devices and computing units. This book, presented in two volumes - Architectures and Applications - therefore celebrates the 20th anniversary of MPSoC, an interdisciplinary forum that focuses on multi-core and multi-processor hardware and software systems. It is this interdisciplinarity which has led to MPSoC bringing together experts in these fields from around the world, over the last two decades. |
| 590 ## - LOCAL NOTE (RLIN) | |
| Local note | John Wiley and Sons |
| Provenance (VM) [OBSOLETE] | Wiley Online Library: Complete oBooks |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Systems on a chip. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Multiprocessors. |
| 650 #6 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Syst�emes sur une puce. |
| 650 #6 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Multiprocesseurs. |
| 650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Multiprocessors |
| Source of heading or term | fast |
| 650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Systems on a chip |
| Source of heading or term | fast |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Andrade, Liliana. |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Rousseau, Fr�ed�eric, |
| Dates associated with a name | 1967- |
| Real World Object URI | https://id.oclc.org/worldcat/entity/E39PCjwJWHpywWjBBg84w9rQbd |
| 758 ## - RESOURCE IDENTIFIER | |
| Relationship information | has work: |
| Label | Multi-processor system-on-chip Architectures 1 (Text) |
| Real World Object URI | https://id.oclc.org/worldcat/entity/E39PCGyjr66rjYJX6qQBwKf6rq |
| Relationship | https://id.oclc.org/worldcat/ontology/hasWork |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Relationship information | Print version: |
| Main entry heading | Andrade, Liliana. |
| Title | Multi-Processor System-On-Chip 1. |
| Place, publisher, and date of publication | Newark : John Wiley & Sons, Incorporated, �2021 |
| International Standard Book Number | 9781789450217 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | <a href="https://onlinelibrary.wiley.com/doi/book/10.1002/9781119818298">https://onlinelibrary.wiley.com/doi/book/10.1002/9781119818298</a> |
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